`include "ascon_define.v"

module `RAM_32B_64
(
    input                                        clk_i,
    input                                        rstn_i,

    input                                        en_i,
    input                                        wen_i,
    input                      [`BUF_ADDR_W-1:0] waddr_i,
    input                  [`AHB_BUS_DATA_W-1:0] wdata_i,

    input                      [`BUF_ADDR_W-1:0] raddr_i,
    output reg             [`AHB_BUS_DATA_W-1:0] rdata_o
);

localparam MEM_DEPTH                             = {`BUF_ADDR_W'b0,1'b1}<<`BUF_ADDR_W;

reg                        [`AHB_BUS_DATA_W-1:0] ram_64 [MEM_DEPTH-1:0];
wire                                             ram_64_en [MEM_DEPTH-1:0];

genvar  i;
generate
for (i=0; i<MEM_DEPTH; i=i+1)
begin : RAM_64_LOOP

assign ram_64_en[i]     = ((i == waddr_i) && (en_i == 1'b1)) ? 1'b1 : 1'b0;

always@(posedge clk_i or negedge rstn_i)
begin : RAM_64_PROG
  if(!rstn_i)
    ram_64[i]           <= `AHB_BUS_DATA_W'd0;
  else if((ram_64_en[i] == 1'b1) && (wen_i == 1'b1))
    ram_64[i]           <= wdata_i;
  else
    ram_64[i]           <= ram_64[i];
end

end

endgenerate

always @(posedge clk_i or negedge rstn_i)
begin : RDATA_O_PROG
  if (rstn_i == 1'b0)
    rdata_o             <= `AHB_BUS_DATA_W'b0;
  else
    rdata_o             <= ram_64[raddr_i];
end

endmodule